RESEARCH TRIANGLE PARK, N.C. - May 25, 2011 - Semiconductor ResearchCorporation (SRC), the world's leading university-research consortiumfor semiconductors and related technologies, and researchers from theUCLA Henry Samueli School of Engineering and Applied Science havedeveloped a new method of design-dependent process monitoring forsemiconductor wafer manufacturing. The advance promises to providesemiconductor chip manufacturing cost and productivity savings up to 15percent, potentially increase profit per chip by as much as 12 percentand ultimately lead to less expensive and higher performing electronicsdevices.
The complexities of semiconductor manufacturing and the challenges ofkeeping pace with Moore's Law are well known within the industry. Modernmanufactured chips exhibit wide power and performance variation thatnecessitate careful screening, and frequency and power tests to screenfor defective chips after chip packaging has been completed areexpensive and time consuming.
Therefore, the industry has significant incentive to prune failed wafersand chips during early stages of manufacturing wherever possible. Whileincreased attention has been given to the design-manufacturinginterface, little has been done to drive design intent intomanufacturing.
That's where UCLA Engineering research comes into play. By using processmonitors on wafer lines tested after the initial manufacturing steps,manufacturers would be able to evaluate early die performance and waferyield estimation. Avoiding going through all the manufacturing steps fora bad wafer can realize the significant cost savings. Avoiding testingfailed die later in the process by leveraging the pruning approach isexpected to save manufacturing costs further, with nearly 70 percent offailed chips pruned with less than a 1 percent yield loss. Though theresults will depend on the design as well as the manufacturing process,the approach is especially useful in early stages of yield ramp for aproduct. An early version of this work appeared in the InternationalConference on Computer-Aided Design in 2010.
"The notion of design-assisted manufacturing is a big change from theway things are done currently," said Puneet Gupta, professor ofelectrical engineering at UCLA who is also a SRC alumni student. "Ourresearch provides the industry a way to not waste resources in producingsilicon wafers that will eventually lose money because chips on them arenot good enough for production. We believe that the cost reductions fromthis and other design-assisted manufacturing methods that we areinvestigating could easily be as much as one full technology node."
Along with semiconductor foundries, design houses would also benefitfrom wafer-cost reductions achieved through the design-dependent processmonitoring approach. Researchers are fine-tuning the approach-includingfinalizing results from a 45 nanometer silicon prototype effort-and hopeto see the industry begin implementing the process within the next fewyears.
"The semiconductor industry has been heavily focused on purelytechnological solutions to scaling, and we've barely scratched thesurface on the potential of design-assisted technology scaling," saidBill Joyner, SRC director of Computer-Aided Design and Test. "Thisresearch leverages design information meaningfully and practically toreduce process control requirements and manufacturing costs."